Computer Architecture - SS1 Digital Technologies Lesson Notes

Computer Architecture - SS1 Digital Technologies Lesson Notes

SS1 Digital Technologies Lesson Notes

Term 1 — Week 2: Computer Architecture & Hardware Operations

What is Computer Architecture?

While computer hardware refers to the physical elements we can see and touch, Computer Architecture is the conceptual design and fundamental operational structure of a computer system. It describes how different hardware components are organized and how they interact with one another to execute instructions and process data.

The Von Neumann Architecture:
Designed by mathematician John von Neumann in 1945, this layout is the universal template for modern computers. It establishes that a computer must store both data and program instructions in the same shared memory unit, processing them sequentially.

Core Components of Computer Architecture

Under the Von Neumann model, a computer system is broken down into four distinct structural divisions:

1. The Central Processing Unit (CPU)

Often called the "brain" of the computer, the CPU executes program instructions. It consists of three internal components:

  • Arithmetic Logic Unit (ALU): Performs all mathematical operations (Addition, Subtraction, Multiplication) and logical decisions (Comparing values, True/False evaluations).
  • Control Unit (CU): The manager of the CPU. It directs the flow of data inside the computer, fetches instructions from memory, decodes them, and tells the ALU and other hardware how to react.
  • Registers: Super-fast, ultra-small internal storage slots right inside the CPU chip used to hold data temporarily while an instruction is being actively calculated.

2. The Memory Unit (Main Memory)

This unit holds instructions and data that the CPU needs immediately to perform a task. It consists of Random Access Memory (RAM) and Read-Only Memory (ROM). In this architecture, data travels continuously between the CPU and Main Memory.

3. Input and Output (I/O) Mechanisms

  • Input Subsystems: Devices like keyboards, mice, scanners, and microphones that convert human actions into digital signals the CPU can understand.
  • Output Subsystems: Devices like monitors, printers, and speakers that translate processed digital results back into physical forms humans can observe.

The Instruction Cycle (Fetch-Decode-Execute)

To run any application (whether opening a web browser or typing a document), the CPU continuously repeats a foundational three-step cycle millions of times per second:

Stage What Happens Inside the Hardware
1. Fetch The Control Unit (CU) retrieves the next program instruction waiting in the system's Main Memory (RAM).
2. Decode The Control Unit breaks down the binary command to figure out exactly what task needs to be performed (e.g., adding two numbers).
3. Execute The CU signals the relevant hardware component (such as the ALU) to carry out the operation, saving the result back into a register or memory.

System Buses: The Internal Highways

Components cannot communicate without physical lines connecting them. Buses are collections of parallel wires used to carry signals across the motherboard. They are divided into three types:

  • Data Bus: Carries the actual data bytes between the CPU, memory modules, and peripheral accessories.
  • Address Bus: Carries information about *where* data needs to go or be fetched from in the memory layout.
  • Control Bus: Carries operational commands and clock timing signals from the Control Unit to keep all components synchronized.

Test Your Knowledge (Week 2 Quiz)

Select the correct answer for each question and click 'Submit' to verify your understanding of Computer Architecture.

1. Which component of the CPU is responsible for making logical comparisons and arithmetic calculations?

2. What is the main structural characteristic of the Von Neumann Architecture?

3. Where are data items held *temporarily* inside the CPU while an instruction is actively being processed?

4. What are the correct three phases of the CPU instruction cycle, in their exact order?

5. Which internal bus is explicitly responsible for transmitting memory location codes?

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